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Honored Contributor
Honored Contributorconfig fpgas with other fpga in AS mode
When I config FPGAs with other FPGA in AS mode,I met troubles below. When I select 3.3v LVTTL as IO STANDARD,the phenomenon is as below. FPGA-1 : the DCLK pin's voltage is about 3.3v FPGA-2 : ...
Altera_ForumHonored Contributor
Honored ContributorBut if you don't connect DATA0 (EPCS data output) at the master FPGA, you aren't able to verify the EPCS programming or check for busy state during programming.
Referring to the origibal problem, I presume that you are pulling nCE high during EPCS access?
