Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- I think, DCLK should achieve full level with 2.5 and 3.3 V standard as well, because the pin is only capacitively loded. --- Quote End --- I also think so,but.... I will do test at other boards to watch the result. besides this,I want to know whether there is any damage to the circuit If I select 2.5v Standard and 16mA current strength(the VCCIO = 3.3v),for that,until now,the main FPGA works normally at FPGAs configuration.