Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

config fpgas with other fpga in AS mode

When I config FPGAs with other FPGA in AS mode,I met troubles below. When I select 3.3v LVTTL as IO STANDARD,the phenomenon is as below. FPGA-1 : the DCLK pin's voltage is about 3.3v FPGA-2 : ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Altera is restricting the current strength with 3.3 and 3.0 V VCCIO for CIII, I guess, it's mostly for reducing signal overshoot. But you probably can damage the FPGA when shorting the output at high current strength.