Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- But if you don't connect DATA0 (EPCS data output) at the master FPGA, you aren't able to verify the EPCS programming or check for busy state during programming. Referring to the origibal problem, I presume that you are pulling nCE high during EPCS access? --- Quote End --- I had pull nCE high and nCONFIG low during EPCS access. the VCCIO is 3.3v,and I set IO Standard to be 2.5v.does it matter? the Max current strength is also diffrent between 2.5v IO Standard and 3.3v IO Standard. (3.3v -> Max current strength = 8mA;2.5v -> Max current strength = 16mA)