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Altera_Forum's avatar
Altera_Forum
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18 years ago

Combining AS and JTAG configuration schemes

Hi all !

I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows

* FPGA : EP3C10E144C7

* VCCIN : 1.2V

* VCCD_PLL1,2 : 1.2V

* VCCA : 2.5V

* VCCIO (for Bank 1 ~ 8) : 3.3V

* VREF of all banks are used as IO ports.

* CLK0 ~ CLK8: are fed by 30MHz oscillator

* Configuration scheme: AS combining JTAG (Fig 10-29 in Configuration Cyclone III device handbook)

* MSEL[2..0] : 010 or 101 (High logic can be 2.5V or 3.3V)

* Pin# 6 of JTAG connector can be removed if we do not want to connect to VCCA (2.5V)

Unfortunately, I could not configure the FPGA via JTAG due to an error "Can't access JTAG chain". I could easily configure the serial configuration device EPCS64 by AS configuration scheme but the FPGA still did not operate after power on. I guessed that the EPCS64 device was not able to configure the FPGA in this case.

Please tell me if there is any mistake in my FPGA setting. I greatly appreciate your help and kindness.

Best Regards,

http://img380.imageshack.us/img380/5334/f1dd2.png (http://imageshack.us)

http://img380.imageshack.us/img380/830/f2im6.png (http://imageshack.us)

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I don't see an error at first look. With VCCIO of 3.3V, the JTAG connector should be supplied with 3.3V as well, to my opinion, but I don't think that this causes the problem. Also, MSEL can have fixed pin straps to AS or fast AS configuration mode, there's no use in having it selectable.

    If the JTAG configuration is functional, AS can be programmed through JTAG using SFL, circuit according to device manual Figure 10-7.

    Also, there's no use in connecting more than 2 clock inputs for a EP3C10, one at each side for the respective PLL. By connecting 8 inputs, your only causing high capacitive load to the oscillator, ground bounce at the FPGA and interferences with other signals.

    Anyway, something must be wrong with your circuit, and it's probably not visible in the schematic. I would check the supply voltages thorougly, there are possible issues with the configuration circuit, if the 2.5V supply is applied before 3.3V.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thank you very much for your opinion.

    I already knew that MSEL can have fixed pin straps for each configuration mode, but in the case of AS mode has been fail, I hope to easily change from AS mode to JTAG mode using SFL. That's why I try to use selectable in my design.

    According to Cyclone III device hanbook, Fig. 10-24 and Fig. 10-25,

    if Vccio is one of 2.5V, 3.0V or 3.3V then the JTAG connector and all pull up resistors for JTAG should be supplied to VCCA (2.5V).

    if Vccio is one of 1.5V, 1.8V then the JTAG connector and all pull up resistors for JTAG should be supplied to Vccio (1.5V or 1.8V).

    So I utilized a voltage of 2.5V for supplying power for JTAG connector.

    Anyway, I will attempt to connect power supplied pin for JTAG to 3.3V and use only one clock input for my design. I hope to sovle such problem as soon as possible.

    Once again, thanks a lot FvM
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hello,

    you're right regarding the 2.5V recommendation in Cyclone III device handbook, I apologize for possibly causing confusion in this point. That's one of the handbook recommendations, I use to ignore, having a clamp diodes as overvoltage protection instead. But I don't think anyway, that the problems are related to using a 2.5 or 3.3 V supply for the JTAG adapter. Both solutions should work. The 2.5V is used by Altera to reduce the maximum voltage of overshoots at the external driven JTAG pins, taking in consideration the properties of existing programming hardware, particularly the USB Blaster.

    The JTAG interface should be operational with any valid configuration mode selected by MSEL and can always take precendence over others. Otherwise, there's something basically wrong with your circuit. In some cases, it may be useful to disable the other configuration method in Quartus programmer options, if the the other configuration interfers with JTAG operation. But you're still able to detect the device in these cases if you didn't.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I'm having the identical problem with my EP3C5E144C8 device. I have another design which uses the EP3C5U256C8 and have no problems with it. The schematics are identical in the two cases except, of course, for the device pinouts.

    One thing I notice is that although the JTAG pins TMS and TDI are pulled up to +3.3V through 10K resistors, they only pull up to about 0.8V (with no cable attached). Also, nConfig is pulled up to +3.3V through a 4.99K resistor, but only pulls up to about 1.1V. Something is clearly wrong. I've gone over the device pinout multiple times but can find no errors.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    No, actually I just discovered the answer on the Altera website. It turns out the the EQFP package has an exposed pad on the bottom that MUST be connected to ground or the device remains in some kind of mysterious reset state. This piece of information is conveniently buried in the fine print in the device pinout documentation. Nice. I'm looking at thousands of dollars in rework costs. Makes me want to take a closer look at Xilinx.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I knowed, that the exposed pad has to be connected, but I wasn't aware of the consequences if omitting the connection. Considering the known ground-bounce problems of TQFP and PQFP packages, one must regard the connected exposed pad as valuable feature, however.

    I agree, that the exposed pad hints in datasheet and pin information should be written in bold letters.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi all,

    Is there anyone consider the ramping time upon power-on for the core voltage (1.2V), VccIO(3.3V) and VccA(2.5V) ? Altera requests that the VccIO, VccINT and VccA must have monotinic rise the their steady state levels, [refer to Fig. 11-3, Cyclone III device handbook].

    Do you think the ramping time causes a serious problem for configuration device ?
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    The main problem is to avoid, during the rise time, an overshoot above the security levels of the supply voltages. That's the main thing to avoid, especially when the "mother" supply voltage comes from a switching regulator.

    The use of dedicated linear regulators for the FPGA and the configuration devices is always a good practice.