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Altera_Forum
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17 years ago

Combining AS and JTAG configuration schemes

Hi all ! I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows * FPGA : EP3C10E144C7 * VCCIN : 1.2V * VCCD_PLL1,2 : 1.2V * VCCA : 2.5V * VC...
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Altera_Forum
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17 years ago

Hello,

you're right regarding the 2.5V recommendation in Cyclone III device handbook, I apologize for possibly causing confusion in this point. That's one of the handbook recommendations, I use to ignore, having a clamp diodes as overvoltage protection instead. But I don't think anyway, that the problems are related to using a 2.5 or 3.3 V supply for the JTAG adapter. Both solutions should work. The 2.5V is used by Altera to reduce the maximum voltage of overshoots at the external driven JTAG pins, taking in consideration the properties of existing programming hardware, particularly the USB Blaster.

The JTAG interface should be operational with any valid configuration mode selected by MSEL and can always take precendence over others. Otherwise, there's something basically wrong with your circuit. In some cases, it may be useful to disable the other configuration method in Quartus programmer options, if the the other configuration interfers with JTAG operation. But you're still able to detect the device in these cases if you didn't.