Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Combining AS and JTAG configuration schemes

Hi all ! I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows * FPGA : EP3C10E144C7 * VCCIN : 1.2V * VCCD_PLL1,2 : 1.2V * VCCA : 2.5V * VC...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thank you very much for your opinion.

I already knew that MSEL can have fixed pin straps for each configuration mode, but in the case of AS mode has been fail, I hope to easily change from AS mode to JTAG mode using SFL. That's why I try to use selectable in my design.

According to Cyclone III device hanbook, Fig. 10-24 and Fig. 10-25,

if Vccio is one of 2.5V, 3.0V or 3.3V then the JTAG connector and all pull up resistors for JTAG should be supplied to VCCA (2.5V).

if Vccio is one of 1.5V, 1.8V then the JTAG connector and all pull up resistors for JTAG should be supplied to Vccio (1.5V or 1.8V).

So I utilized a voltage of 2.5V for supplying power for JTAG connector.

Anyway, I will attempt to connect power supplied pin for JTAG to 3.3V and use only one clock input for my design. I hope to sovle such problem as soon as possible.

Once again, thanks a lot FvM