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Altera_Forum
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17 years ago

Combining AS and JTAG configuration schemes

Hi all ! I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows * FPGA : EP3C10E144C7 * VCCIN : 1.2V * VCCD_PLL1,2 : 1.2V * VCCA : 2.5V * VC...
Altera_Forum's avatar
Altera_Forum
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17 years ago

The main problem is to avoid, during the rise time, an overshoot above the security levels of the supply voltages. That's the main thing to avoid, especially when the "mother" supply voltage comes from a switching regulator.

The use of dedicated linear regulators for the FPGA and the configuration devices is always a good practice.