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Altera_Forum
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18 years ago

Combining AS and JTAG configuration schemes

Hi all ! I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows * FPGA : EP3C10E144C7 * VCCIN : 1.2V * VCCD_PLL1,2 : 1.2V * VCCA : 2.5V * VC...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Hi all,

Is there anyone consider the ramping time upon power-on for the core voltage (1.2V), VccIO(3.3V) and VccA(2.5V) ? Altera requests that the VccIO, VccINT and VccA must have monotinic rise the their steady state levels, [refer to Fig. 11-3, Cyclone III device handbook].

Do you think the ramping time causes a serious problem for configuration device ?