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Altera_Forum
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17 years ago

Combining AS and JTAG configuration schemes

Hi all ! I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows * FPGA : EP3C10E144C7 * VCCIN : 1.2V * VCCD_PLL1,2 : 1.2V * VCCA : 2.5V * VC...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

No, actually I just discovered the answer on the Altera website. It turns out the the EQFP package has an exposed pad on the bottom that MUST be connected to ground or the device remains in some kind of mysterious reset state. This piece of information is conveniently buried in the fine print in the device pinout documentation. Nice. I'm looking at thousands of dollars in rework costs. Makes me want to take a closer look at Xilinx.