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Altera_Forum
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17 years ago

Combining AS and JTAG configuration schemes

Hi all ! I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows * FPGA : EP3C10E144C7 * VCCIN : 1.2V * VCCD_PLL1,2 : 1.2V * VCCA : 2.5V * VC...
Altera_Forum's avatar
Altera_Forum
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17 years ago

I don't see an error at first look. With VCCIO of 3.3V, the JTAG connector should be supplied with 3.3V as well, to my opinion, but I don't think that this causes the problem. Also, MSEL can have fixed pin straps to AS or fast AS configuration mode, there's no use in having it selectable.

If the JTAG configuration is functional, AS can be programmed through JTAG using SFL, circuit according to device manual Figure 10-7.

Also, there's no use in connecting more than 2 clock inputs for a EP3C10, one at each side for the respective PLL. By connecting 8 inputs, your only causing high capacitive load to the oscillator, ground bounce at the FPGA and interferences with other signals.

Anyway, something must be wrong with your circuit, and it's probably not visible in the schematic. I would check the supply voltages thorougly, there are possible issues with the configuration circuit, if the 2.5V supply is applied before 3.3V.