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Altera_Forum
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18 years ago

Combining AS and JTAG configuration schemes

Hi all ! I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows * FPGA : EP3C10E144C7 * VCCIN : 1.2V * VCCD_PLL1,2 : 1.2V * VCCA : 2.5V * VC...
Altera_Forum's avatar
Altera_Forum
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17 years ago

I knowed, that the exposed pad has to be connected, but I wasn't aware of the consequences if omitting the connection. Considering the known ground-bounce problems of TQFP and PQFP packages, one must regard the connected exposed pad as valuable feature, however.

I agree, that the exposed pad hints in datasheet and pin information should be written in bold letters.