Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity of data and clock recovery). From this data there are recovered 125 MHz pulses every 44.1 kHz (sync pulses). I would like to recover this 44.1 kHz clock from the bit stream. (for audio purposes - to match the clock of the data - if internal 44.1 clock is used form the generator there are some bad effects in the sound). My questions are: 1) Can i simply feed those pulses into the second PLL module to recover the data ? 2) Are there any other considerations that i should think about ? thanks madness123

The bitstream encoding details aren't very clear in your post. But generally speaking, regular Altera PLLs aren't designed for CDR purposes. They require a continuous reference clock to synchronize on it. Depending on required clock tolerance, there may be a chance to implement a CDR scheme based on PLL dynamic phase shift in user logic. Newer FPGA families with hardware SERDES are also implementing a software CDR feature.

Hi FvM, The Clock and Data Recovery works fine, perhaps it's not done with best practises but it works with no problems. I have the question about pulses that are generated from this data (their source doesn't really matter) -> can i recover a clock from pulses occuring approx. every (1/44100)s. best regards madness

As far as I understand, the 125 MHz is already recovered from the data stream. Then the 44.1 kHz detection problem hasn't to do with clock recovery, it's about detecting a sync pattern. What's specific to the 44.1 kHz pattern that allows to distinguish it from the data stream? By the way, what's the involved FPGA family

If I understood you, you already have pulses at 44.1KHz possibly generated from a counter or sync pulse. You want to generate 44.1KHs from data itself. I suggest you use simple averaging filter(just accumulator) to remove high frequency. i.e. add up samples for some suitable total that will build up then come down to zero as the stream stops at zero. You should then get sort of triangular pulses at 44.1KHz then apply a comparator to get cleaner pulses.

Hi, the family is Cyclone III - 5k LE. As kaz has written i already have 44.1k sync pulses from data itself. I put the data bits into the shift register, and then: sync_detect : process (clk_125_in, shift_register) begin if clk_125_in'event and clk_125_in = '1' then if ((shift_register(14 downto 5) = "1100010001") and (shift_register(4 downto 0) /= "11000")) THEN synchronized <= '1'; else synchronized <= '0'; end if; end if; end process sync_detect; So my questions are once again :). 1) From the data i get synchronized pulses every 44.1kHz. I would like to and have to make a clock from this, I even would have to if neccessary multiply it by 2 or 4 to get 88.2 or 176.4k for different modes. That's why i'm thinking about PLL. Can i simply put them in the PLL or should i do smth with them as kaz has written. 2) I had ocasionally problems with fan-outing this signal to the other parts of my design - i suppose that due to CDR there were some problems. Could i simply put there another signal like synchronized2 to double up the logic, but to get the second signal and not to mess with the synchronized? Or am i saying stupid things?:) best regards

Clock recovery from signle 125MHz pulses with PLL

25 Replies

Altera_Forum
Honored Contributor
14 years ago
Hi kaz,
thanks, i thought about using this sync pulses to make a new "clock", let's say to invert this new clock when sync pulse occurs, that would give me me 22.05 kHz clock....

but you're right it's too slow anyway... :)

perhaps i could use this new "clock" and latch the data every rising AND falling edge ?

don't really know how to get the higher rates :}

best regards
Altera_Forum
Honored Contributor
14 years ago
I wonder, if it's possible to make the 125 MHz clock an integer multiple of 44.1 kHz at the sender? This would simplify things a lot.

Otherwise a software PLL (ADPLL) can be used to track the 44.1 kHz.

If 44.1 kHz is not generated as integer multiple of 125 MHz but is an unrelated external clock or generated by a fractional divider, the sync signal will be still send with 125 MHz resolution. Consequently there will be a jitter of the sync signal relative to the ideal 44.1 clock as well as the recovered one.
Altera_Forum
Honored Contributor
14 years ago
Hi,
thanks FvM. The way it works is:
On the sender side, when rising edge of 44.1k occurs it transmits with 125MHz clock 64 channels of audio and after that it starts sending 10 bit sync pattern. After transmitting the 10 bit pattern it checks if the next rising edge occured, if not it stars sending another 10bit bit pattern, otherwise next 64 channels. You're right there is a jitter.

That's the way i implemented it in my device, it works fine with RME (german audio firm) PC card - they're recovering the clock from my device (sound quality is good). When i use on their side their internal 44.1k clock and in my device 44.1k clock, there are some clicks in the sound.

That's why i would like to implement this 44.1k clock recovery from my sync pattern. So do you say that ADPLL is a way to go ?:) i will look into it, thanks :)

best regards
madness
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Hi kaz,
thanks, i thought about using this sync pulses to make a new "clock", let's say to invert this new clock when sync pulse occurs, that would give me me 22.05 kHz clock....

--- Quote End ---

Don't invert just at sync but also half way through using a counter. Set counter to zero at sync then count up 22.05k clocks and reinvert.

Though I will use sync as clock enable rather than clock as you are gating it.

Altera_Forum

Honored Contributor

14 years ago

Hi,

what do you mean by gating? I was thinking about smth like:

process (clk_125_in, synchronized)
 begin
  if rising_edge(clk_125_in) then
        if synchronized = '1' then
    clock_recovery_counter <= (others => '0');
        else 
            -- counting logic
       end if;                    
  end if;
 end process;

regards

Altera_Forum
Honored Contributor
14 years ago
I mean if you generate clock at 41.2KHz as such from inversion then it is a clock that is generated by gating as opposed to PLL. There is nothing wrong with this generation but then I will avoid using it as clock for edge triggering those registers. This means I will use your system clock(125Mhz) to trigger edges and use sync itself as clock enable on those registers. So I don't need to convert sync to clock in the first place.

Altera_Forum

Honored Contributor

14 years ago

Hi,

thanks :)

so i could simply use

process (clk_125_in, synchronized)
 begin
  if rising_edge(clk_125_in) then
        if synchronized = '1' then
        -- rest of the code - used as "rising edge" of the "recovered clock"

and that's all : )

i will still have to think about 176.4k and using ADPLL :)

thanks

Altera_Forum
Honored Contributor
14 years ago
The core of an ADPLL would be a NCO generating the 176.4 kHz clock. Using a PI loop filter, it can ideally average the jitter of the sync signal to +/- 0.5 * 8ns, provided there's no additional jitter source than sampling the input signal at 125 MHz.
Altera_Forum
Honored Contributor
14 years ago
Hi,
I opened megafunction wizard and found NCO. Are there any restrictions to using this megafunction ? there is smth about licensing it. I wasn't able to find any usefull into about that.

best regards
Altera_Forum
Honored Contributor
14 years ago
Yes you need to pay a license for it, or use it in evaluation mode (i.e. with the USB blaster connected all the time, and you can't flash your project)

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Clock recovery from signle 125MHz pulses with PLL

25 Replies

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