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Honored Contributor
Honored ContributorClock recovery from signle 125MHz pulses with PLL
Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_ForumHonored Contributor
Honored ContributorI mean if you generate clock at 41.2KHz as such from inversion then it is a clock that is generated by gating as opposed to PLL. There is nothing wrong with this generation but then I will avoid using it as clock for edge triggering those registers. This means I will use your system clock(125Mhz) to trigger edges and use sync itself as clock enable on those registers. So I don't need to convert sync to clock in the first place.
