Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Clock recovery from signle 125MHz pulses with PLL

Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

thanks :)

so i could simply use 

process (clk_125_in, synchronized)
 begin
  if rising_edge(clk_125_in) then
        if synchronized = '1' then
        -- rest of the code - used as "rising edge" of the "recovered clock"

and that's all : )

i will still have to think about 176.4k and using ADPLL :)

thanks