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Altera_Forum
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13 years ago

Clock recovery from signle 125MHz pulses with PLL

Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
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Altera_Forum
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13 years ago

I wonder, if it's possible to make the 125 MHz clock an integer multiple of 44.1 kHz at the sender? This would simplify things a lot.

Otherwise a software PLL (ADPLL) can be used to track the 44.1 kHz.

If 44.1 kHz is not generated as integer multiple of 125 MHz but is an unrelated external clock or generated by a fractional divider, the sync signal will be still send with 125 MHz resolution. Consequently there will be a jitter of the sync signal relative to the ideal 44.1 clock as well as the recovered one.