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Altera_Forum
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13 years ago

Clock recovery from signle 125MHz pulses with PLL

Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
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Altera_Forum
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13 years ago

Hi,

thanks FvM. The way it works is:

On the sender side, when rising edge of 44.1k occurs it transmits with 125MHz clock 64 channels of audio and after that it starts sending 10 bit sync pattern. After transmitting the 10 bit pattern it checks if the next rising edge occured, if not it stars sending another 10bit bit pattern, otherwise next 64 channels. You're right there is a jitter.

That's the way i implemented it in my device, it works fine with RME (german audio firm) PC card - they're recovering the clock from my device (sound quality is good). When i use on their side their internal 44.1k clock and in my device 44.1k clock, there are some clicks in the sound.

That's why i would like to implement this 44.1k clock recovery from my sync pattern. So do you say that ADPLL is a way to go ?:) i will look into it, thanks :)

best regards

madness