Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Clock recovery from signle 125MHz pulses with PLL

Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi kaz,

thanks, i thought about using this sync pulses to make a new "clock", let's say to invert this new clock when sync pulse occurs, that would give me me 22.05 kHz clock....

but you're right it's too slow anyway... :)

perhaps i could use this new "clock" and latch the data every rising AND falling edge ?

don't really know how to get the higher rates :}

best regards