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Honored Contributor
Honored ContributorClock recovery from signle 125MHz pulses with PLL
Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_ForumHonored Contributor
Honored ContributorHi,
what do you mean by gating? I was thinking about smth like:process (clk_125_in, synchronized)
begin
if rising_edge(clk_125_in) then
if synchronized = '1' then
clock_recovery_counter <= (others => '0');
else
-- counting logic
end if;
end if;
end process;
