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Honored Contributor
Honored ContributorClock recovery from signle 125MHz pulses with PLL
Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi kaz, thanks, i thought about using this sync pulses to make a new "clock", let's say to invert this new clock when sync pulse occurs, that would give me me 22.05 kHz clock.... --- Quote End --- Don't invert just at sync but also half way through using a counter. Set counter to zero at sync then count up 22.05k clocks and reinvert. Though I will use sync as clock enable rather than clock as you are gating it.
