Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Clock recovery from signle 125MHz pulses with PLL

Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The core of an ADPLL would be a NCO generating the 176.4 kHz clock. Using a PI loop filter, it can ideally average the jitter of the sync signal to +/- 0.5 * 8ns, provided there's no additional jitter source than sampling the input signal at 125 MHz.