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Honored ContributorClock recovery from signle 125MHz pulses with PLL
Hi,
I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity of data and clock recovery). From this data there are recovered 125 MHz pulses every 44.1 kHz (sync pulses). I would like to recover this 44.1 kHz clock from the bit stream. (for audio purposes - to match the clock of the data - if internal 44.1 clock is used form the generator there are some bad effects in the sound). My questions are: 1) Can i simply feed those pulses into the second PLL module to recover the data ? 2) Are there any other considerations that i should think about ? thanks madness12325 Replies
Altera_ForumThe bitstream encoding details aren't very clear in your post. But generally speaking, regular Altera PLLs aren't designed for CDR purposes. They require a continuous reference clock to synchronize on it. Depending on required clock tolerance, there may be a chance to implement a CDR scheme based on PLL dynamic phase shift in user logic. Newer FPGA families with hardware SERDES are also implementing a software CDR feature.
- Altera_Forum
Hi FvM,
The Clock and Data Recovery works fine, perhaps it's not done with best practises but it works with no problems. I have the question about pulses that are generated from this data (their source doesn't really matter) -> can i recover a clock from pulses occuring approx. every (1/44100)s. best regards madness - Altera_Forum
As far as I understand, the 125 MHz is already recovered from the data stream. Then the 44.1 kHz detection problem hasn't to do with clock recovery, it's about detecting a sync pattern.
What's specific to the 44.1 kHz pattern that allows to distinguish it from the data stream? By the way, what's the involved FPGA family - Altera_Forum
If I understood you, you already have pulses at 44.1KHz possibly generated from a counter or sync pulse. You want to generate 44.1KHs from data itself.
I suggest you use simple averaging filter(just accumulator) to remove high frequency. i.e. add up samples for some suitable total that will build up then come down to zero as the stream stops at zero. You should then get sort of triangular pulses at 44.1KHz then apply a comparator to get cleaner pulses. - Altera_Forum
Hi,
the family is Cyclone III - 5k LE. As kaz has written i already have 44.1k sync pulses from data itself. I put the data bits into the shift register, and then:
So my questions are once again :). 1) From the data i get synchronized pulses every 44.1kHz. I would like to and have to make a clock from this, I even would have to if neccessary multiply it by 2 or 4 to get 88.2 or 176.4k for different modes. That's why i'm thinking about PLL. Can i simply put them in the PLL or should i do smth with them as kaz has written. 2) I had ocasionally problems with fan-outing this signal to the other parts of my design - i suppose that due to CDR there were some problems. Could i simply put there another signal like synchronized2 to double up the logic, but to get the second signal and not to mess with the synchronized? Or am i saying stupid things?:) best regardssync_detect : process (clk_125_in, shift_register) begin if clk_125_in'event and clk_125_in = '1' then if ((shift_register(14 downto 5) = "1100010001") and (shift_register(4 downto 0) /= "11000")) THEN synchronized <= '1'; else synchronized <= '0'; end if; end if; end process sync_detect; - Altera_Forum
The filter method I proposed apply only if there frequency component in data stream at 44.1KHz but it doesn't look that way now. If you are detecting actual pattern for sync then you got it from data already. Or do you mean your sync is not at 44.1KHz? I need more clarity please
- Altera_Forum
Yea kaz, you're right there are not higher frequency components, sync pulses occur every 44.1kHz. Sync is exactly at 44.1 kHz.
I need to recover from that 44.1 or 88.2 or 176.4 kHz clocks. I haven't tried it yet, cause i'm doing smth else right now, i'm just asking if it's possible or there will be some problems. I would like to use a PLL module for that. best regards - Altera_Forum
You don't need PLL, you got the pulses at 44.1KHz. To get clock at 44.1KHz I assume you mean regular half duty cycle pulses like the usual clock patterns.
Well you can do that without PLL but you don't even need. It is safer to use the sync as clock enable on clock 125MHz itself. For 2x or 4x modes I assume the sync will produce the new rate. If not you can use counter for that. So you have no problem really. Regarding fanout you only get such problems with very large designs and normally compiler does the duplication but can readily duplicate manually as you suggested if you think it is going to help but I have feeling your design may have some other problems. - Altera_Forum
Yea the CDR is not perfect : ) but it works - sometimes when i use SignalTap and use too many elements it doesn't work - after decreasing SignalTap LE and memory usage and recompilation it works fine.
The protocol i'm using is madi, it sends with one line 64 audio channels in one frame. There are as you may think 44.1kHz frames. So one stereo audio channel takes 2 audio channels from the link. To get a higher data rate - 88.2 ad 176.4 one stero audio channel takes 4 for 88.2 and 8 for 176.4. So i can get the data needed for 176.4 but i still got 44.1kHz pulses. I'll try to use PLL next week and write here how it went: ) best regtards - Altera_Forum
PLLs work with clean clock inputs and can't work at slow speeds. So I don't have much hope on that.
