Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorClock recovery from signle 125MHz pulses with PLL
Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_ForumHonored Contributor
Honored ContributorAs far as I understand, the 125 MHz is already recovered from the data stream. Then the 44.1 kHz detection problem hasn't to do with clock recovery, it's about detecting a sync pattern.
What's specific to the 44.1 kHz pattern that allows to distinguish it from the data stream? By the way, what's the involved FPGA family
