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Altera_Forum
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14 years ago

Clock recovery from signle 125MHz pulses with PLL

Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
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Altera_Forum
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14 years ago

The bitstream encoding details aren't very clear in your post. But generally speaking, regular Altera PLLs aren't designed for CDR purposes. They require a continuous reference clock to synchronize on it. Depending on required clock tolerance, there may be a chance to implement a CDR scheme based on PLL dynamic phase shift in user logic. Newer FPGA families with hardware SERDES are also implementing a software CDR feature.