Clock recovery from signle 125MHz pulses with PLL

You don't need PLL, you got the pulses at 44.1KHz. To get clock at 44.1KHz I assume you mean regular half duty cycle pulses like the usual clock patterns.

Well you can do that without PLL but you don't even need. It is safer to use the sync as clock enable on clock 125MHz itself. For 2x or 4x modes I assume the sync will produce the new rate. If not you can use counter for that. So you have no problem really. Regarding fanout you only get such problems with very large designs and normally compiler does the duplication but can readily duplicate manually as you suggested if you think it is going to help but I have feeling your design may have some other problems.