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Honored Contributor
Honored ContributorClock recovery from signle 125MHz pulses with PLL
Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_ForumHonored Contributor
Honored ContributorIf I understood you, you already have pulses at 44.1KHz possibly generated from a counter or sync pulse. You want to generate 44.1KHs from data itself.
I suggest you use simple averaging filter(just accumulator) to remove high frequency. i.e. add up samples for some suitable total that will build up then come down to zero as the stream stops at zero. You should then get sort of triangular pulses at 44.1KHz then apply a comparator to get cleaner pulses.
