Clock recovery from signle 125MHz pulses with PLL

Hi,

the family is Cyclone III - 5k LE.

As kaz has written i already have 44.1k sync pulses from data itself.

I put the data bits into the shift register, and then:

sync_detect : process (clk_125_in, shift_register)
 begin
  if clk_125_in'event and clk_125_in = '1' then
        if ((shift_register(14 downto 5) = "1100010001") and (shift_register(4 downto 0) /= "11000")) THEN
           synchronized <= '1';
        else 
           synchronized <= '0';
       end if;                    
  end if;
 end process sync_detect;

So my questions are once again :).

1) From the data i get synchronized pulses every 44.1kHz. I would like to and have to make a clock from this, I even would have to if neccessary multiply it by 2 or 4 to get 88.2 or 176.4k for different modes.

That's why i'm thinking about PLL. Can i simply put them in the PLL or should i do smth with them as kaz has written.

2) I had ocasionally problems with fan-outing this signal to the other parts of my design - i suppose that due to CDR there were some problems.

Could i simply put there another signal like synchronized2 to double up the logic, but to get the second signal and not to mess with the synchronized? Or am i saying stupid things?:)

best regards