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Altera_Forum
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13 years ago

Clock recovery from signle 125MHz pulses with PLL

Hi, I have a circuit that uses one PLL to recover data and clock from a single bitstream. This PLL is fed with 125 MHz clock, on it's output there is 375 MHz clock (which is used for the circuity ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Yea the CDR is not perfect : ) but it works - sometimes when i use SignalTap and use too many elements it doesn't work - after decreasing SignalTap LE and memory usage and recompilation it works fine.

The protocol i'm using is madi, it sends with one line 64 audio channels in one frame. There are as you may think 44.1kHz frames.

So one stereo audio channel takes 2 audio channels from the link.

To get a higher data rate - 88.2 ad 176.4 one stero audio channel takes 4 for 88.2 and 8 for 176.4.

So i can get the data needed for 176.4 but i still got 44.1kHz pulses.

I'll try to use PLL next week and write here how it went: )

best regtards