Honored ContributorHi
I have 2 verilog designs. Each of them is correct in simulation but when I simulate both of then in one schematic file, the result of simulation is incorrect. I think this problem is because of input clock to 2 different block. Am I right? If yes, what should I do to solve this problem? Thanks
Honored ContributorSo, are these two designs set up so the output of one is used as the input to the other? Or, are they two different code blocks that should do the same thing in parallel? In the combined simulation, which block outputs the wrong values for the known good inputs? And, are the failed outputs the wrong values, or X's?
Honored ContributorMake sure everything that needs to be in the sensitivity lists are in the sensitivity lists and each signal has a reset condition. If the output of one block drives the next, propagating X's can cause problems, ensure all signals being driven out have proper reset conditions to avoid X's. Alternatively, you can assign an initial condition to the signal to avoid X's.
Honored ContributorHi
2 blocks are parallel and no one trrigers the other. When I simulate each of them, the result of simulation is correct. But simulation of 2 blocks in parallel cuase an incorrect answer. For example the result is not stable in positive edge of the clock and also the result is not valid after 1 period of the clock.Honored ContributorHi,
as I wrote in NIOS forum, probably you have not "clocked" enough your code, that means there are too long combinatorial expressions :eek: . What about the gobal assignment for the clock? Did you turned on the design assistant? Have you checked if the time requirements are respected? Hope this can help you. Reguards CesareHonored ContributorDear c augusto
Please explain your comments for example about global assignment of clock and design assistant.Honored ContributorHi,
go info NIOS Forum, you will find your answer...Honored ContributorAre you doing a functional simulation or a timing simulation?
Honored ContributorHi
Timing simulation.Honored ContributorTry running a functional simulation and make sure the logic is correct. If you get the correct result with the functional sim, you can then run the timing sim and see where the difference is.
If each block that simulates correctly has its own independent clock, you need to look at clock boundary crossings. Look for warning messages about combinational loops when compiling in Quartus. Make sure you have contraints for the clocks and those contraints are met using your targeted device.
