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Altera_Forum's avatar
Altera_Forum
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18 years ago

Clock Buffer

Hi I have 2 verilog designs. Each of them is correct in simulation but when I simulate both of then in one schematic file, the result of simulation is incorrect. I think this problem is because of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi

2 blocks are parallel and no one trrigers the other.

When I simulate each of them, the result of simulation is correct. But simulation of 2 blocks in parallel cuase an incorrect answer. For example the result is not stable in positive edge of the clock and also the result is not valid after 1 period of the clock.