Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorClock Buffer
Hi I have 2 verilog designs. Each of them is correct in simulation but when I simulate both of then in one schematic file, the result of simulation is incorrect. I think this problem is because of...
Altera_ForumHonored Contributor
Honored ContributorMake sure everything that needs to be in the sensitivity lists are in the sensitivity lists and each signal has a reset condition. If the output of one block drives the next, propagating X's can cause problems, ensure all signals being driven out have proper reset conditions to avoid X's. Alternatively, you can assign an initial condition to the signal to avoid X's.
