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Altera_Forum's avatar
Altera_Forum
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18 years ago

Clock Buffer

Hi I have 2 verilog designs. Each of them is correct in simulation but when I simulate both of then in one schematic file, the result of simulation is incorrect. I think this problem is because of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

So, are these two designs set up so the output of one is used as the input to the other? Or, are they two different code blocks that should do the same thing in parallel? In the combined simulation, which block outputs the wrong values for the known good inputs? And, are the failed outputs the wrong values, or X's?