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Altera_Forum's avatar
Altera_Forum
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18 years ago

Clock Buffer

Hi I have 2 verilog designs. Each of them is correct in simulation but when I simulate both of then in one schematic file, the result of simulation is incorrect. I think this problem is because of...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

as I wrote in NIOS forum, probably you have not "clocked" enough your code, that means there are too long combinatorial expressions :eek: .

What about the gobal assignment for the clock?

Did you turned on the design assistant?

Have you checked if the time requirements are respected?

Hope this can help you.

Reguards

Cesare