Clock Buffer

Try running a functional simulation and make sure the logic is correct. If you get the correct result with the functional sim, you can then run the timing sim and see where the difference is.

If each block that simulates correctly has its own independent clock, you need to look at clock boundary crossings. Look for warning messages about combinational loops when compiling in Quartus. Make sure you have contraints for the clocks and those contraints are met using your targeted device.