Arria II GX + DIMM = no more than 12 HSTL/SSTL output or bi-directional pins are allo

I have the same issue in my design which targets an EP2AGX190FF35C5 (1152 pins). In my case, I have two DDR2 interfaces (16-bit) on the same edge of the chip.

The problem is usually brought up by not correctly defining the output enable groups for the bidirectional memory data path. If you follow the suggested design flow for the DDR controller, tcl files containing the respective settings are automatically imported to the design assignments. The point is, that all bidrectional data and dqs pins of a DDR RAM are set as input or output simultaneously. Thus, the limitation for maximum allowed number of output or bidirectional pins in a bank does not apply. Quartus is using the attribute output enable group to mark those pins, that are driving simultaneoulsy.

FYI: I ended up fitting my (64-bit) SO-DIMM in a 780-pin EP2AGX45DF29C6. I span the interface over banks 5A, 6A, 7A and 8A.

As far as I see, a 64-Bit DIMM can be operated from 3 IO banks in the 572 and 780-pin package. The limiting factor is the number of availiable DQS groups. The said "limitation of 12 SSTL signals per I/O bank" is caused by incomplete pin assignments.

I ran into the same issue. This is documented in http://www.altera.com/literature/dp/arria-ii-gx/pcg-01007.pdf . Look at note 12 on page 7. There is also a correction/clarification for that note somewhere else, but I forget where.

I didn't try with differential DQS. To see, what's the problem with 572-pin Arria II, I would have to implement a test design. I was originally referring to the reported "12 SSTL signal limitation" which is known as a problem of missing OE-group assignments. It may be the case, that Arria II has additional restrictions, that don't allow to implement a 64-Bit RAM interface with 572-pin package. If so, it would be a chip design or Quartus flaw.