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Honored Contributor
Honored ContributorArria II GX + DIMM = no more than 12 HSTL/SSTL output or bi-directional pins are allo
I'm trying to get my EP2AGX45 (572 package) Arria II GX to interface with a DIMM. I've run into an apparent limitation of 12 SSTL signals per I/O bank. It seems i will have to move up to the top devi...
Altera_ForumHonored Contributor
Honored ContributorI have the same issue in my design which targets an EP2AGX190FF35C5 (1152 pins). In my case, I have two DDR2 interfaces (16-bit) on the same edge of the chip.
Based on the external memory interface documentation, I could put up to six DDR2 interfaces (16-bit) on each edge of the FPGA... With the error we have, no-one will achieve to fit six DDR2 interfaces on the same edge, Quartus will say that there are too many output/bidir pins in the same I/O module... Something's wrong here, either the doc has boosted the numbers, or there is a way to fix this error in Quartus... Martin
