Arria II GX + DIMM = no more than 12 HSTL/SSTL output or bi-directional pins are allo

I have the same issue in my design which targets an EP2AGX190FF35C5 (1152 pins). In my case, I have two DDR2 interfaces (16-bit) on the same edge of the chip.

Based on the external memory interface documentation, I could put up to six DDR2 interfaces (16-bit) on each edge of the FPGA...

With the error we have, no-one will achieve to fit six DDR2 interfaces on the same edge, Quartus will say that there are too many output/bidir pins in the same I/O module... Something's wrong here, either the doc has boosted the numbers, or there is a way to fix this error in Quartus...

Martin