Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI didn't try with differential DQS. To see, what's the problem with 572-pin Arria II, I would have to implement a test design. I was originally referring to the reported "12 SSTL signal limitation" which is known as a problem of missing OE-group assignments. It may be the case, that Arria II has additional restrictions, that don't allow to implement a 64-Bit RAM interface with 572-pin package. If so, it would be a chip design or Quartus flaw.
I implemented however a DIMM interface with only two 1.8V banks of 1120-pin Arria, which should give an almost comparable number of available memory pins.