Arria II GX + DIMM = no more than 12 HSTL/SSTL output or bi-directional pins are allo

The problem is usually brought up by not correctly defining the output enable groups for the bidirectional memory data path. If you follow the suggested design flow for the DDR controller, tcl files containing the respective settings are automatically imported to the design assignments. The point is, that all bidrectional data and dqs pins of a DDR RAM are set as input or output simultaneously. Thus, the limitation for maximum allowed number of output or bidirectional pins in a bank does not apply. Quartus is using the attribute output enable group to mark those pins, that are driving simultaneoulsy.