ALTLVDS rx timing issue

Hello,

May I know what is your input clock frequency?

Hello

the input clock frequency is 96Mhz

Thx

Hello,

Thank you for your confirmation. Does it come from the dedicated reference clock pin within the I/O bank?

Which device is this and you are using which version of Quartus Prime?

Regards,

Aqid

Hello,

I wish to follow up. Do you have any update?

Regards,

Aqid

Hello sorry for the delay

i was in vacancy

the quartus version is quartus prime 24.1

yes the clk is dedicated clock : BANK 2F pin DD47

Thx

Apologies not asking this earlier. Which device does this LVDS IP target?

Hello targeting the agilex7 f series : AGIB027R31B1E1V

Hello,

We have tried creating an example design with the parameters shown and saw no timing failures. The worst-case slack for the timing path listed was 2.853.

The large discrepancy between the slack we are seeing and the slack you are seeing is mostly likely due to you having a different clock relationship because their PLL clocks are configured incorrectly.

Ensure that the VCO frequency and the outclk frequency/phase shift/duty cycle settings on the external PLL driving the LVDS IP match the settings listed in the Clock Resource Summary in the LVDS IP.

Also, please ensure that the reference clock frequency on the PLL IP matches the Actual inclock frequency on the LVDS IP as the settings listed in the Clock Resource Summary tab may not be attainable with the wrong reference clock frequency.

Regards,

Aqid

If it’s not caused by incorrect clock configuration, other possible causes include using an outdated SDC due to using an old Quartus version (19.2 or older) or a placement/routing issue.

I dont see any issue on the design ... iam using : quartus prime 24.1 ..

any idea ?