ALTLVDS rx timing issue

Hello,

We have tried creating an example design with the parameters shown and saw no timing failures. The worst-case slack for the timing path listed was 2.853.

The large discrepancy between the slack we are seeing and the slack you are seeing is mostly likely due to you having a different clock relationship because their PLL clocks are configured incorrectly.

Ensure that the VCO frequency and the outclk frequency/phase shift/duty cycle settings on the external PLL driving the LVDS IP match the settings listed in the Clock Resource Summary in the LVDS IP.

Also, please ensure that the reference clock frequency on the PLL IP matches the Actual inclock frequency on the LVDS IP as the settings listed in the Clock Resource Summary tab may not be attainable with the wrong reference clock frequency.

Regards,

Aqid