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kikoss's avatar
kikoss
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

ALTLVDS rx timing issue

Hello I have hold timing issue on the ALTLVDS RX inside logic ..

I have an ALTLVDS RX ip confgiured like that

i get hold timing issues in timequest :

-0.019 u_tx_rx_wrapper|u_adc_controller|lvds_0|core|arch_inst|rx_channels[1].dpa_fifo.serdes_dpa_inst~rx_internal_reg u_tx_rx_wrapper|u_adc_controller|lvds_0|core|arch_inst|rx_channels[1].dpa_fifo.des[4].rxout_ufi~ufi_write_reg u_tx_rx_wrapper|u_tx_rx_pll|iopll_0_fclk0 u_tx_rx_wrapper|u_tx_rx_pll|iopll_0_loaden0

why its occur ? its inside the altera IP ..

Thx

kikoss

Fpga Devkit
Generic Io

13 Replies

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  • kikoss's avatar
    kikoss
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    I reduce my design to the minimum.

    And seems that the issue occurs when we choose more than 2 channels

    when running with 2 channels, no timing issue, when running with 3 channels, I get hold time issue ...

    @AqidAyman_Intel seems there its an altera issue ..

    wait for help from @altera ..

    THX

    kikoss

  • kikoss's avatar
    kikoss
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    to be more precise : the issue occur when we have at least 3 channels and when the pll is external one ..

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    I will contact you through email since I need to share with you some of the snapshots.

    Need your help to check the inbox.


    Regards,

    Aqid