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kikoss's avatar
kikoss
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

ALTLVDS rx timing issue

Hello I have hold timing issue on the ALTLVDS RX inside logic .. I have an ALTLVDS RX ip confgiured like that i get hold timing issues in timequest : -0.019 u_tx_rx_wrapper|u_adc_...
Fpga Devkit
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kikoss's avatar
kikoss
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

to be more precise : the issue occur when we have at least 3 channels and when the pll is external one ..