AqidAyman_Altera
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Re: Differential Signal Transmitter on Agilex 5 FPGA Modular Dev Kit
Hi, It is expected that Quartus don't allow you to use 1.2V bank supply with TDS transmitter pins. Based on the datasheet, transmitter pin can only use 1.3V TDS. And it is also expected to be compatible with LVDS Receiver (for certain data rates, you can DC coupled to interface the TDS TX with LVDS RX). For more information, you may refer to this Application Note from below link: AN 555: https://docs.altera.com/r/docs/776775/current/an-555-true-differential-signaling-termination-and-biasing-for-agilextm-7-m-series-agilextm-5-and-agilextm-3-fpgas/minimum-vod-lvds-transmitter-interfaces-with-1.3-v-tds-receiver Regards, Aqid3Views0likes0CommentsRe: Agilex 7I-Series Device Errata and User Guide: Why my answers are deleted all the time:
Hi CyberSam035 I really regret with the experience you are facing on the deletion of the message. We are investigating this issue. However, can you confirm if you already register for MyAltera account and manage to download the file? As I saw your reply in the original thread. Regards, Aqid2Views0likes0CommentsRe: Cyclone 10 LP's Extended Industrial parts
Hello MAC_Yossi, 1. Refers to this KDB, it mentions that there is no difference between Industrial and Extended Industrial in device OPN. Both will be used "I" as the letter to indicate the Operating Temperature. 2. If the device OPN is listed as Extended Industrial grade, then you may choose the same OPN in EPE. 3. After selecting the device, if the device is supported for Extended Industrial grade, you may check it on Assignments - > Settings -> Temperature. This is the example for 21.1 Standard version:4Views0likes0CommentsRe: MAX 10 FPGA POR trip Levsl and tRAMP
Yes, if your battery ramp exceeds the specs of the MAX10 tRAMP, then the device may remain held in POR and fail to configure. This is mentioned in the same document you refer: Unfortunately, you need to ensure that the power supply ramp time meets the specification to allow the nSTATUS to be asserted.9Views0likes0CommentsRe: LVDS TX/RX Pin Assignment Error in Quartus – Unable to Resolve
Hi Hari, Can you try to remove all the pin assignments? If this passes the compilation, then you should follow the pin placement suggested by the fitter, and then it should be good. It might be the issue with your differential pin and PLL pin placement. Refer guideline below: https://docs.altera.com/r/docs/721819/25.3.1/agilextm-7-lvds-serdes-user-guide-f-series-and-i-series/pin-placement-for-differential-channels Regards, Aqid3Views0likes0Comments