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AqidAyman_Altera
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Re: Agilex 5 D-Series HVIO IOPLL runtime reconfiguration: C0 write succeeds, but output remains 100 MHz
Hello, The locked signal remaining high while 0x080[2] is asserted strongly indicates the active-PLL reset register is not being accessed. Since this is a production device, HVIO core_avl interface requires word addressing. Although the register transactions complete, the displayed addresses are the documented byte offsets. Please refer to the following KDB and repeat the sequence using word addresses: Why does Agilex® 5 FPGA and Agilex® FPGA 3 HVIO PLL fail to lock after reconfiguration? | Altera Community - 354904 If the output still stays at 100 MHz after confirming word addresses at the physical HVIO interface, please provide the stp capture and the transaction log for further checking. Regards, Aqid4Views0likes0CommentsRe: Mentor Graphics PADS-compatible footprint/library file # A5ED065BB32AI4S
Hi amol, At present, the officially published PCB footprint is available in Cadence Allegro .dra format. The internal team do not provide a validated Mentor Graphics PADS-compatible library file. The recommended approach is to convert the .dra file using an approved, licensed CAD conversion flow or recreate the footprint in PADS using the official footprint, ball coordinates, and package mechanical drawing as the controlling references. I regret that I cannot provide a validated Mentor Graphics PADS-compatible file at this time. We hope the references above allow your layout work to proceed without further delay. Regards, Aqid3Views0likes0CommentsRe: Mentor Graphics PADS-compatible footprint/library file # A5ED065BB32AI4S
Hi Amol, I am able to find the below file for this part number: Schematic Symbol: Cadence* Capture CIS schematic symbol for A5ED065B (B23A, B32A Packages) • Viewer • Altera Documentation and Resources Center PCB Footprint: Agilex™ 5 Device Allegro* PCB Footprint for B32A (1591) Package - Advance • Viewer • Altera Documentation and Resources Center Regards, Aqid6Views0likes1CommentRe: COD (Country of Diffusion ) for part# '5M40ZE64I5N'
Hi Vraj, I got the information which as below: 5M40ZE64I5N is qualified in two wafer fabs, so the COD is either USA or Taiwan. If you can share privately the shipment documents and label, I can help to identify the actual COD of the part that is shipped to the customer. Regards, Aqid15Views0likes2CommentsRe: Agilex 3 PLL in Source Synchronous mode ?
Hi, I am able to get the design compiled successfully by letting Quartus selecting the clock input pin. You need to remove the I/O standard assigned first. Unfortunately, the compilation is failed if I assigned to the specific pin you mentioned (AT9). Unless, if you promote it as a global clock, then the compilation is passed. Below settings in .qsf in your project file: set_location_assignment PIN_AT9 -to CLOCK0_50 -comment IOBANK_6E set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to CLOCK0_50 -entity pll_bug set_instance_assignment -name GLOBAL_SIGNAL ON -to CLOCK0_50 Regards, Aqid5Views0likes1Comment