AqidAyman_Altera
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Re: Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)
Hello YY, Yes, I agree with Frank. I also did not found a direct duration time between the phasestep and phasedone as you requested. However, the relationship between the Scanclk and VCO frequency may affect the phasedone duration time. Below is the article that may help you: Why does phasedone always appear high after asserting phasestep? | Altera Community - 341015 What is the relationship between PHASEDONE and SCANCLK in the ALTPLL Intel® FPGA IP? | Altera Community - 347897 Regards, Aqid4Views0likes0CommentsRe: Cyclone 5 SoC FPGA Bank Supply Prerequisite
Hi Brian, The Cyclone® V Pin Connection Guidelines state: “Connect these pins (VCCIO) to a power supply” Your test results align with the expectations, where when you left VCCIO floating, it can cause programming failure. For best and safest device hardware configuration, always connect VCCIO to the correct supply for every I/O bank, including BANK 5A/5B. Reference: Cyclone® V GX, GT, E, SX, ST and SE Device Family Pin Connection Guidelines Regards, Aqid7Views0likes1CommentRe: Download links not working
Hi Mario, Apologies for the delayed response. The internal team is working on the broken links. Please refer to the new link below: Cyclone® V zip file for Differential Pad Placement Mapping files The link was also updated in the documents. Thanks for your help in pointing this out. Regards, Aqid6Views0likes0CommentsRe: Different FPGA model shows: DEV-AGM039EA
Hello Takashi, I tried on the same development kit (DK-DEV-AGM039EA) that is available and found the same situation as what your customer reported. When I use the Quartus Programmer "Auto Detect", it will show AGME039R47A. However, you may ignore this, as this device has the same Device ID as AGMF039R47A. Quartus will auto-choose which device comes first in its list that has the same Device ID detected. Refer here: https://docs.altera.com/r/docs/683748/current/agilextm-7-jtag-boundary-scan-testing-user-guide/device-id When I try to program the file with the .sof file available in the Installer Package, it programs successfully. So, there is no issue. The development kit should have the correct device OPN, which is AGMF039R47AC. Regards, Aqid1View0likes1CommentRe: Different FPGA model shows: DEV-AGM039EA
Hello Takashi, Firstly, I apologies for the delay response. Regarding your issue here, from my understanding, you suspected the device on the board is having a different OPN that what was showing in the catalog and the website. Here are my feedback and suggestions: 1- The device on the development kit with the ordering code: DK-DEV-AGM039EA should be AGMF039R47A1E1VC based on the user guide. 2- What is the Quartus version are you using? Can you try using 25.1.1 Pro Edition version? 3- Can you try to program the device with any provided .sof file located in the Installer Package of the development kit? For example, you can find bts_config.sof located in the \DK-DEV-AGM039EA_25.1.1b125_final\DK-DEV-AGM039EA_25.1.1b125\examples\bts_config\output_files directory. 4- Can you share the serial number of the development kit? If needed, you can privately share to me via private message. Regards, Aqid14Views0likes2Comments