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AqidAyman_Altera
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Re: Request for details<46206 >
Hi Santosh, We can share the Country of Diffusion (COD) or Country of Fabrication (COF) information. As for now, there is no specific documentation or webpage provide this info as per my understanding. So, I will need the full device part number in order to check internally and provide you with the information. Regards, Aqid3Views0likes0CommentsRe: GPIO access in max10 BSP
Hi, The BSP automatically includes the matching software support for peripherals in the Nios processor system. The GPIO hardware must first exist in the Platform Designer system. For memory-mapped GPIO, add the PIO (Parallel I/O) IP in Platform Designer. Connect its Avalon Memory-Mapped agent interface to the Nios processor data master, export the PIO conduit to the top level, and assign the corresponding FPGA pins in Quartus Prime. References: Embedded Peripherals IP User Guide: PIO Core Quartus Prime Standard Edition User Guide: Creating a System with Platform Designer Quartus Prime Standard Edition User Guide: Connecting System Components7Views0likes0CommentsRe: Investigation of HIGH-Level Voltage Fluctuations on MAX 10 3.3 V LVTTL Output Signals
I understand. Thank you for the clarification. From the MAX 10 side, there are several signal integrity levers worth examining if you have the chance to do it as a software-only change without board respins required. Two immediate knobs to try: Reduce drive strength. The output buffer for each MAX 10 I/O pin has a programmable current strength control. For 3.3 V LVTTL, the available settings are 8 mA and 4 mA. Programmable Current Strength Try to drop from 8 mA to 4 mA. Enable slow slew rate. Slow slew rate reduces system noise and crosstalk, but adds a nominal delay to the rising and falling edges. MAX 10 General Purpose I/O User Guide If timing margin permits, this is a low-risk change that you can experiment.6Views0likes0CommentsRe: Agilex 5 RCOMP_GTS connection change and its effect on HVIO input pins
Hi Mario, Altera does not publish a detailed internal circuit description of the GTS-to-HVIO path. At the level we can share publicly: this is a product architecture requirement on Agilex 5 and Agilex 3 devices with GTS. When RCOMP_GTS on a side is left floating and that side's GTS supplies are powered, the HVIO pins in the HVIO bank adjacent to that GTS bank are not configured correctly during device configuration. The device still configures and enters user mode, but those HVIO pins (input or bidirectional) can look stuck high or otherwise non-functional. That is also why: - Instantiating no transceiver in the Quartus design does not avoid the issue. The board power / RCOMP connection condition is what matters. - The impact is limited to the HVIO bank adjacent to the affected GTS side, as stated in the Knowledge Base article.7Views1like1CommentRe: Agilex 5 E-Series 065B Premium Dev Kit - is FPGA_3V3_SDA/SCL driven by an HPS I2C controller?
Hello, Please refer to my answer below: 1. Is that correct, and does the kit's reference design connect an HPS I2C or a soft I2C IP to these pins? <ANS> The dev kit schematic confirms FPGA_3V3_SCL/SDA is the "QSFP1, QSFP2, and EEPROM I2C interface FPGA", meaning those signals are wired to FPGA fabric I/O, not to the dedicated HPS IOA/IOB pads. The published HPS baseline for this kit also does not connect an HPS I2C controller or a soft I2C master to those pins. Reference: Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide, https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium-065b/gsrd/ug-gsrd-agx5e-premium-065b/ 2. How do I confirm which controller drives these pins in Quartus Prime software and at runtime in Linux? <ANS> In Quartus Prime: Search the QSF or Pin Planner for FPGA_3V3_SDA and FPGA_3V3_SCL. No location assignment means nothing in that project drives the bus. In Platform Designer, open the HPS Pin Mux tab. If I2C0 or I2C1 is set to FPGA, follow i2c0_sda_i, i2c0_sda_oe, i2c0_scl_in_clk, and i2c0_clk_clk (or the I2C1 equivalents) to the top-level ports. Those conduits tied to the Bank 5A pins mean the HPS I2C controller is the master. If a soft I2C IP has its SDA and SCL ports connected to those same pins, that IP is the master. In Linux, on the board booted from that image, run i2cdetect -l. An enabled HPS I2C controller shows up as a DesignWare adapter (i2c_designware). A soft master shows up only when that fabric IP and its device-tree node are in the image. However, on the enablement baseline, neither adapter is attached to FPGA_3V3_SCL/FPGA_3V3_SDA. Thank you.1View0likes0CommentsRe: Investigation of HIGH-Level Voltage Fluctuations on MAX 10 3.3 V LVTTL Output Signals
May I know what is your main concern on this voltage fluctuations? I checked the datasheet of the external device you connected and found that 2.8 V is still a valid high for the DS90CR287. The TxIN pins are LVTTL/LVCMOS inputs, and the datasheet specifies VIH at 2.0 V minimum (DS90CR287, SNLS056, https://www.ti.com/lit/ds/symlink/ds90cr287.pdf). Correct me if I'm wrong.7Views0likes2CommentsRe: Leakage Current in MAX 10 Bank 1A (ADC Bank)
Hi y-fujiwara, 10M08DCF256I7G is a dual-supply compact device and does not include the ADC, so Bank 1A is a normal I/O bank. The ADC is on the analog ordering codes (DA or SA). I confirmed this in 10M08DC pin-out, Bank 1A has no ADC pins. It is a normal I/O bank, with the same leakage specification as Bank 8. So, the lower voltage on Bank 1A is not caused by ADC pin leakage on this device. Your divider (10 kohm / 3.6 kohm) has a source resistance of about 2.65 kohm. Bank 8 at 3.17 V is essentially the unloaded divider voltage (about 3.18 V). Bank 1A at 3.06 V is about 0.11 V lower, which implies about 42 uA into that pin. That is above the +/-10 uA normal limit, so Bank 1A is drawing extra current in this condition. Please check these three items: VCCIO of Bank 1A compared with Bank 8. If the pin voltage is above that bank's VCCIO, the clamp diode is on. The datasheet states that a higher current can be observed when the diode is on. Both banks are fully powered when you measure. The +/-10 uA values are for normal operation and can be different during power-up. The Quartus assignment for the Bank 1A pin: input only, with bus-hold, weak pull-up, and weak pull-down off, and the pin is not also driven as an output. If Bank 1A VCCIO is at least 3.3 V, the clamp is off, and the pin is a plain input, about 42 uA is outside the published +/-10 uA limit. References: The DC and DA ordering codes are in the MAX 10 FPGA Device Overview (683658), in the ordering-information section: https://docs.altera.com/r/docs/683658/current/max-10-fpga-device-overview/max-10-device-ordering-information The feature table that lists the integrated ADC only under the Analog option is here: https://docs.altera.com/r/docs/683658/current/max-10-fpga-device-overview/max-10-device-feature-options0Views0likes1CommentRe: Agilex 3 PLL in Source Synchronous mode ?
Yes, I agree that for this board, the validated RGMII Gigabit Ethernet through a source-synchronous IOPLL is not available with the current pinout. Remaining options on this kit are limited to whatever Terasic documents for their Ethernet example (if they provide that), or other interfaces that are actually brought out, such as MIPI as you noted.4Views0likes0Comments