AqidAyman_Altera
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Re: Agilex 5 reconfigurable PLL - emif
Hi Lenz, The minimum supported phase shift step is fixed by the VCO frequency (e.g., at 1 GHz VCO, the step is 125 ps). If the requested phase shift (e.g., 100 ps) does not align with this step size, the PLL cannot accurately deliver it. When multiple shifts are performed, quantization and rounding errors can accumulate, leading to some shifts being much larger than intended (i.e., the “occasional large jump” that you observed). Regards, Aqid2Views0likes0CommentsRe: How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?
Hi Steve, Please refer to the following explanation of the Warning that you see. https://microsites.altera.com/microsites/psg_microsites_migration/quartushelp/current/index.htm#msgs/msgs/wcio_design_pin_assigned_to_clkusr_location.htm Based on the explanation, we would infer that Quartus detected transceivers in your design. If transceivers are used in your design, then you need NOT do a pin assignment in the .qsf. However, it is must to provide a clock of 100-125 MHz at its input. No need to constraint it in the .sdc. If you are not using transceivers, not using HMC, and not using this pin as a user-supplied configuration clock, instead want to use it as a GPIO, then you need to assign the logic port to the device CLKUSR pin location and constraint the pin in .sdc. We hope this information helps. Regards, Aqid7Views0likes1CommentRe: Agilex 3 PLL in Source Synchronous mode ?
Hello, Thank you for reaching out to us. This looks to me either a pin resources issue or hardware limitation issue. Can you share with me the use case design where I can replicate the error from my side? I need to check it first. Preferably in .QAR file. If you need to share it privately, let me know. Regards, Aqid12Views0likes1CommentRe: MAX10 and CycloneV GX 25'C、35'C MTBF
Currently, the FIT and MTBF are on the product details page (search by OPN at altera.com, then the results will include “product details”), but for 70C Tj. An example: https://www.altera.com/products/fpga/cyclone/v/gx/5cgxc3-u19/5CGXFC3B6U19C7N10Views0likes0CommentsRe: Cyclone 10 LP Device Pin Match
Dear Brian, Q1: according to 10cl006.xls and 10cl025.xls. For 256 BGA this is not drop in replaceable? >>> Based on the device overview document, 10CL006 and 10CL025 for the U256 package are included in the vertical migration path. Q2: Any document or pin table that can easily make the design variant possible? >>> Other than the pinout file, you can verify the pin migration compatibility by using the Pin Migration View window in Quartus. You can refer here: Device Migration Planning29Views0likes1Comment