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kikoss's avatar
kikoss
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

ALTLVDS rx timing issue

Hello I have hold timing issue on the ALTLVDS RX inside logic .. I have an ALTLVDS RX ip confgiured like that i get hold timing issues in timequest : -0.019 u_tx_rx_wrapper|u_adc_...
Fpga Devkit
Generic Io
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


Thank you for your confirmation. Does it come from the dedicated reference clock pin within the I/O bank?


Which device is this and you are using which version of Quartus Prime?


Regards,

Aqid