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kikoss's avatar
kikoss
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

ALTLVDS rx timing issue

Hello I have hold timing issue on the ALTLVDS RX inside logic .. I have an ALTLVDS RX ip confgiured like that i get hold timing issues in timequest : -0.019 u_tx_rx_wrapper|u_adc_...
Fpga Devkit
Generic Io
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

If it’s not caused by incorrect clock configuration, other possible causes include using an outdated SDC due to using an old Quartus version (19.2 or older) or a placement/routing issue.