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Occasional Contributor

2 years ago

ALTLVDS rx timing issue

Hello I have hold timing issue on the ALTLVDS RX inside logic .. I have an ALTLVDS RX ip confgiured like that i get hold timing issues in timequest : -0.019 u_tx_rx_wrapper|u_adc_...

Fpga Devkit

Generic Io

AqidAyman_Altera

Regular Contributor

1 year ago

Apologies not asking this earlier. Which device does this LVDS IP target?

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ALTLVDS rx timing issue

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