Good day,I had a working EMIF IP set up and connected to the HPS in Quartus 24.2. I then upgraded to Quartus 24.3.1 and now can no longer get the EMIF IP to compile without errors. I replaced the old EMIF IP with the HPS EMIF IP (emif_io96b_hps). I can generate the HDL from Platform Designer without any errors. I get the following error when compiling:Error(17821): Netlist error at hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd(275): port 's1_axi4_wuser' of width 64 cannot connect to actual of width 32Details:Quartus 24.3.1 is used with all IP upgraded.I connect the io96b0_to_hps conduits of the HPS and HPS EMIF together. The channel 1 axi4 wuser is 32 bits wide for both the HPS and EMIF:I am using LPDDR4 with configuration of 2x16 (8Gbit).In hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd the wuser signals are all of width 32.I am unable to see where the 64-bit wide signal is and how to fix it.C:/Firmware/CheetahTacticalRouter/tactical-router-fw/tactical_router_fpga/quartus/ip/hps_system/hps_system_emif_io96b/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy/synth/ip/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4/synth/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd

Can you show your connections and parameter settings in PD?

Good day,Platform Designer Connections:EMIF Parameters:HPS Parameters: I added the last two images for the HPS Parameters as attachments, because they did not want to load here. The system compiled without errors in Quartus 24.2. I had to upgrade the HPS and EMIF IP, the remaining HPS related IP did not change.Let me know if you require any further information.

It looks OK. Is this an example design you generated or a design you built yourself? Perhaps try generating the example design and then customize that as needed if you built this manually.

Good day,This is not an example design; no example design exists for this. The Quartus 24.2 design was based on the development kit and worked. This seems to be either an issue with the latest Quartus (24.3.1) or the updated IP Cores for this version.If I remove the EMIF then it complains about other HPS pins, such as USB2 not being connected, however it is not something that is done outside of the IP core and the settings show it is connected. This is why I think there may be issues with the HPS IP.

No, I mean a customized example design you generate from the IP Parameter Editor that creates a whole project for you based on the settings you specify in the Parameter Editor. This is a good way to create a complete design quickly.

Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

26 Replies

AdzimZM_Altera
Regular Contributor
11 months ago
Hi Nicole,

Thank you for your feedback.

I will try to replicate the issue again with the file that you have shared.

Regards,
Adzim
mfiorenza
New Contributor
11 months ago
I have attached my project below for reference if it will help. My project only has the Agilex5 HPS IP, HPS EMIF IP, and FPGA EMIF IP. Both LPDDR4s are the same. HPS EMIF IP compiles successfully but the FPGA EMIF IP leaves me with the error (s0_axi4_wuser) shown above.
s0_axi4_wuser_emif_error_24_3_1_102.qar3.4 MB
MM-ATH
Occasional Contributor
10 months ago
We had similar problems - if we have checked Compile to VHDL (in Platform Designer/generate HDL). if ve have checked Compile to Verilog, problem gone away.
AdzimZM_Altera
Regular Contributor
10 months ago
Hi,

The issue can be replicated if the EMIF IP is used VHDL code.

There is a parameter where the axi4_wuser width is determined.
If it does not use the NoC, the width is set to 64 for axi4_wuser.

The parameter can be found in the EMIF IP file path *_emif_io96b_lpddr4_0\emif_io96b_lpddr4_200\synth\*_emif_io96b_lpddr4_0_emif_io96b_lpddr4_200_*.sv.

localparam PORT_AXI_USER_WIDTH = 64,
localparam PORT_AXI_NOC_USER_WIDTH = 32,
localparam PORT_AXI_S0_USER_WIDTH = PHY_USE_NOC_INTF ? PORT_AXI_NOC_USER_WIDTH : PORT_AXI_USER_WIDTH,

Change the PORT_AXI_USER_WIDTH = 64 to 32 can resolve this error message.
Can you try to change the port width to 32 and check the compilation again?

Regards,
Adzim
- MM-ATH
  Occasional Contributor
  10 months ago
  Thanks Adzim,
  Yes, this change leads to good compilation on our testing design.
- Nicole04
  Occasional Contributor
  10 months ago
  Hi Adzim,
  Thank you for looking into this problem. I see multiple files containing this portion. Should it be changed at all cases?
  I changed it at all places and then received the following error:
  Error(13224): Verilog HDL or VHDL error at io0_emif_bank2a_fpga_emif_io96b_lpddr4_200_tq2i7vi_atom_inst_hmc_wide.sv(1041): index 32 is out of range [31:0] for 'ruser'
  
  Kind regards,
  Nicole
- Nicole04
  Occasional Contributor
  10 months ago
  Hi Adzim,
  Thank you for the update. Will an IP core update be made?
  
  My one design works, but another gives a file inclusion error:
  Error(16827): Verilog HDL error at emif_io96b_hps_0_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4_emif_io96b_cal_200_hpbproa.sv(17): cannot open include file cal_io96b_interface.svh
  
  Kind regards,
  Nicole
AdzimZM_Altera
Regular Contributor
10 months ago
Hi Nicole,

I don't think you need to change in all files.
Make the change in the top IP file should be okay.

Try to regenerate the IP file again and make the change in the path that I have provided.

Regards,
Adzim
Nicole04
Occasional Contributor
10 months ago
Hi Adzim,
The width error seems to be fixed in the Quartus 25.1 version.
I do however still get the inclusion error. I have tried regenerating the IP, cleaning the project and regenerating again, but the error persists. The included file does exist.

Error(16827): Verilog HDL error at emif_io96b_hps_0_emif_io96b_hps_300_4hwut5y_emif_0_lpddr4_emif_io96b_lpddr4_300_ljjag6i.sv(17): cannot open include file emif_io96b_interface.svh

Kind regards,
Nicole
- Nicole04
  Occasional Contributor
  10 months ago
  I was able to get a temporary work around, but hopefully this can be fixed in the future.
  I was able to compile the design when the path is made shorter. I had to place my quartus folder directly on the C drive of my PC, because the path for the LPDDR4 EMIF IP is very long.
  Is there a way to shorten the names used in the IP folders?
AdzimZM_Altera
Regular Contributor
10 months ago
Hi Nicole,

I'm glad that your issue has been resolved.
We will try to improve the IP file name to avoid this issue in future.

Currently we cannot set the IP file name shorter automatically.
Manually edit the IP file name is possible.

Regards,
Adzim

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Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

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