Forum Discussion
Honored ContributorA problem with using DCFIFO (lpm_fifo)
Hello!
In my design I have a 8bit x 4 words dual-clock fifo component (LPM_FIFO+) and I observe a very strange behaviour or the wrfull output signal. Since I have fifo 4 word-deep I expect the wrfull signal go high on a 4th write I am surprised when the wrfull goes high right after the first write cycle. I have tried to enable all the protection circuits available in this component but still not get the good results. The fifo component is on the data input to the uart transmitter... At this point I would appreciate a fresh pair of eyes look from somebody on the forum - maybe there is something obvious wrong and I do not see it. Can you help me? Here is the fragment of the circuit with the fifo component: http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view¤t=fifo.jpg And here simulation with the wrfull signal going high after first write: http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view¤t=simul.jpg Please note, wrfull signal is visible in the simulation as TX_EMPTY and is inversed. Any ideas where and what to check? Thanks!12 Replies
Altera_ForumThe virtual JTAG doesn't use the Nios CPU and should be suitable to connect to a FIFO.
I've never used it though, so I can't help you further than that.- Altera_Forum
I tried to use NIOS several times, complete failure and frustration.
Can you please help me to use just a FIFO, and find a way to connect it to a PC? My Project is at risk for wasting too much time trying with Nios. I appreciate all input and suggestions. Thanks. - Altera_Forum
Could the virtual jtag megafunction (http://www.altera.com/literature/ug/ug_virtualjtag.pdf) help you? It will require some work to set up, but you can sent/receive vectors to your designs through that interface.
- Altera_Forum
NO, I am not using Nios, I also do not use any communication CORE. The physical connection I have right now is the USB that is used to upload the SOF file or the flash with programs, as well as debugging, etc. I was intending to use it as my USB connection and get a USB core, but I learned that it doesn't connect to the FPGA pins, and I have to get an extra USB connection. My problem is that the only HSMC connection available is occupied with a board from BiTec that I am using in my desgin, there is no other connection else the 10 PINs of the boundary scan available. I tried to find any product in the market to expand the HSMC to add another board to include USB, I couldn't find any so far. Can I survive with just a FIFO and UART or serial connection? My design needs to reconfigured at run-time, but few bytes and no speed is necessary.
- Altera_Forum
Are you using a Nios CPU in your design? What connections do you have with your PC?
- Altera_Forum
Hi All, I need help to figure out how to connect the lpm_fifo to the outside world, to a PC? I have Cyclone III Starter board, and I don't see any pins available else the 10 pins boundary scan.
I am a beginner so I don't really know how to do so. - Altera_Forum
I noticed that wrusedw[] is more acurate, but if the fifo component is internaly protected from overflow than as soon as wrfull is asserted no more bytes are written. So it trully means that if I want to store 4 bytes I need to setup 7-8 bytes fifo component... that is wrong. Looks like I am forced to build 8 words fifo and use wrusedw[2] to indicate 4th write.
I see the "'last three words of the FIFO may not be usable because of the synchronization pipelines between the clock domains" in the mega wizard configuration window... I missed this before - thanks. I am using original Cyclone device, we can call it Cyclone I :) Not sure why the behaviour of the fifo component would depend on the device I am using... especially if I am using flip-flops and not memory to build the fifo component. Do you know why? - Altera_Forum
And when you created the FIFO ( I guess you are using Stratix?), you might have noticed that 'last three words of the FIFO may not be usable because of the synchronization pipelines between the clock domains'!!!
You could increase depth of the FIFO if you need to support 4 byte storage.. But in Stratix II and other devices, the behavior is different and you can get the advantage of full depth. - Altera_Forum
you could use wrusedw for more accurate full indication.
Also, I hope you are using aclr to reset the FIFO pointers initially, or else it will not work. - Altera_Forum
The rdclk is there as well, it is much slower frequency and it is not visible on the simulation fragment.
The fifo component works in the TX part of the uart circuit. The wrclk is the CPU clock, very fast compared to the rxclk, which is the baud clock. Whole CPU write cycle happens between edges of the baud clock (rdclk). Is there any restrictions on frequency difference between these two clocks? Also, what is strange, I got the sample waveforms from this component and they not look good: http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view¤t=uart_lpm_fifo_tx3_wave0.jpg This is 4 words fifo and the wrfull goes already high after 3rd wrclk edge during write sequence... This sample waveform is wrong or I am missing something? What is going on?
