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Altera_Forum's avatar
Altera_Forum
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16 years ago

A problem with using DCFIFO (lpm_fifo)

Hello! In my design I have a 8bit x 4 words dual-clock fifo component (LPM_FIFO+) and I observe a very strange behaviour or the wrfull output signal. Since I have fifo 4 word-deep I expect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

And when you created the FIFO ( I guess you are using Stratix?), you might have noticed that 'last three words of the FIFO may not be usable because of the synchronization pipelines between the clock domains'!!!

You could increase depth of the FIFO if you need to support 4 byte storage..

But in Stratix II and other devices, the behavior is different and you can get the advantage of full depth.