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Honored Contributor
Honored ContributorA problem with using DCFIFO (lpm_fifo)
Hello! In my design I have a 8bit x 4 words dual-clock fifo component (LPM_FIFO+) and I observe a very strange behaviour or the wrfull output signal. Since I have fifo 4 word-deep I expect...
Altera_ForumHonored Contributor
Honored ContributorI noticed that wrusedw[] is more acurate, but if the fifo component is internaly protected from overflow than as soon as wrfull is asserted no more bytes are written. So it trully means that if I want to store 4 bytes I need to setup 7-8 bytes fifo component... that is wrong. Looks like I am forced to build 8 words fifo and use wrusedw[2] to indicate 4th write.
I see the "'last three words of the FIFO may not be usable because of the synchronization pipelines between the clock domains" in the mega wizard configuration window... I missed this before - thanks. I am using original Cyclone device, we can call it Cyclone I :) Not sure why the behaviour of the fifo component would depend on the device I am using... especially if I am using flip-flops and not memory to build the fifo component. Do you know why?
